The present invention relates to a trellis decoder and its associated method for performing decoding of a trellis encoded modulated signal.
ANNEX B of the ITU-T RECOMMENDATION J.83 is the American standard for digital cable televisions. This ANNEX B standard employs trellis encoded modulation which is a combination of an error correcting code and a modulation process, wherein the error correcting code comprises a punctured code with a code rate of 4/5 produced from a convolutional code with a code rate of 1/2 and the modulation process is either 64 QAM (Quadrature Amplitude Modulation) or 256 QAM.
A typical conventional trellis decoder intended for use in decoding the above-described type of trellis encoded modulated signal will be explained by making reference to FIG. 7. This conventional trellis decoder comprises (a) a branch metric arithmetic circuit 701 for deciding, from an input received signal, the maximum likelihood between a received signal point and a subset signal point and for outputting a branch metric and a subset decision signal, (b) an ACS (Add Compare Select) circuit 702 for performing arithmetic operations to compute, from the branch metric output from the branch metric arithmetic circuit 701, a path metric according to a trellis diagram and for outputting a path selection signal for selection of a path having a high likelihood, (c) a first memory circuit 703 for storing the subset decision signal output from the branch metric arithmetic circuit 701, (d) a second memory circuit 704 for storing the path selection signal output from the ACS circuit 702, (e) a traceback circuit 705 for performing, from a first to a second time point, traceback of the subset decision signal and the path selection signal and for outputting, based on the traceback results, a subset decoding signal and an encoded bit decoding signal, and (f) a reverse conversion circuit 706 for outputting, from the obtained subset decoding signal, a non-encoded bit decoding signal.
The operation of the conventional trellis decoder constructed in the way described above will be explained by making reference to FIGS. 8, 9 and 10.
FIG. 8 shows signal points on a complex plane specified by a real number axis (an I axis) and an imaginary number axis (a Q axis) in 64 QAM. Each of these signal points comprises a respective signal of six bits (i.e., bits C5, C4, C3, C2, C1, and C0). The two bits C5 and C4 are I component non-encoded bits. The bit C3 is an I component encoded bit. The two bits C2 and C1 are Q component non-encoded bits. Finally, the bit C0 is a Q component encoded bit. Determination of the subset is made by the I component encoded bit C3 and the Q component encoded bit C0 in each signal point. In this example, 64 signal points are classified into four subsets.
FIGS. 9 and 10 show examples of the I component subset signal points. In the example of FIG. 9, 32 black dots represent respective subset signal points with a value C3=0. On the other hand, in the example of FIG. 10, 32 black dots represent respective subset signal points with a value C3=1. The received signal passing through a transmission channel may become a signal with interference such as noise due to the condition of the transmission channel and therefore its signal points do not always correspond to the signal points as shown in FIGS. 8-10. To cope with this, the branch metric arithmetic circuit 701 firstly decides in which of four decision regions I00, I01, I02, and I03 (FIG. 9) a received signal point R(Ri, Rq) is situated. The branch metric arithmetic circuit 701 further decides in which of four decision regions I10, I11, I12, and I13 the aforesaid received signal point R is situated. Then, the branch metric arithmetic circuit 701 outputs the decision results as an I component subset decision signal for storage in the first memory circuit 703.
Here, the four decision regions of the subset signal points (FIG. 9) are determined as follows.
xe2x88x92P3 Decision Region (I00): Ri less than xe2x88x92P2
xe2x88x92P1 Decision Region (I01): xe2x88x92P2xe2x89xa6Ri less than xe2x88x92P0
P0 Decision Region (I02): xe2x88x92P0xe2x89xa6Ri less than P1
P2 Decision Region (I03): P1xe2x89xa6Ri
On the other hand, the four decision regions of the subset signal points (FIG. 10) are determined as follows.
xe2x88x92P2 Decision Region (I10): Ri less than xe2x88x92P1
xe2x88x92P0 Decision Region (I11): xe2x88x92P1xe2x89xa6Ri less than P0
P1 Decision Region (I12): P0xe2x89xa6Ri less than P2
P3 Decision Region (I13): P2xe2x89xa6Ri
In the examples (FIGS. 9 and 10), the branch metric arithmetic circuit 701 decides that the received signal point R is situated in the decision region I00 (xe2x88x92P3) relating to subset signal points with a value C3=0 and in the decision region I10 (xe2x88x92P2) relating to subset signal points with a value C3=1. Further, based on a branch metric calculated from a Euclidean distance between the subset signal point with a value C3=0 (xe2x88x92P3) derived from the subset signal point decision and the received signal point R (such a branch metric will be hereinafter referred to as the branch metric 0), and based on a branch metric calculated from a Euclidean distance between the subset signal point with a value C3=1 (xe2x88x92P2) derived from the subset signal point decision and the received signal point R (such a branch metric will be hereinafter referred to as the branch metric 1), the ACS circuit 702 performs arithmetic operations to compute a path metric according to a trellis diagram and outputs a path selection signal for selection of a path having a high likelihood for storage in the second memory circuit 704.
In, FIGS. 9 and 10, the description has been made in terms of I component subset signal points. In addition, also with respect to the Q component, the maximum likelihood between the received signal point R and the Q component subset signal point with a value C0=0 and the maximum likelihood between the received signal point R and the Q component subset signal point with a value C0=1 are determined thereby to output a subset decision signal and a path selection signal for storage in the first memory circuit 703 and in the second memory circuit 704, respectively.
The traceback circuit 705 performs traceback of the subset decision signal stored in the first memory circuit 703 and the path selection signal stored in the second memory circuit 704 from a first to a second time point. Then, the traceback circuit 705 outputs an I component/Q component subset decoding signal from the traceback of the subset decision signal and an I component/Q component encoded bit decoding signal from the traceback of the path selection signal. Further, the reverse conversion circuit 706 converts the subset decoding signal to provide a non-encoded bit decoding signal.
The above-described trellis decoder configuration however suffers the problem that the branch metric arithmetic circuit 701 has to perform subset signal point decision on every decision region in all quadrants. This increases the circuit scale of compare circuits incorporated in the arithmetic circuit 701. Further, the first memory circuit 703 has to store the subset decision signal having information content about all the quadrants. This also produces the problem that the circuit scale of the memory circuit 703 becomes larger.
Accordingly, an object of the present invention is to provide a trellis decoder and its associated method capable of accomplishing reductions in the circuit scale.
In order to achieve the object, in accordance with the present invention, when performing decoding of a trellis encoded modulated signal, a received signal point is converted into a converted signal point situated in any one of all the quadrants on a complex plane specified by an I and a Q axis. Then, the result of subset signal point decision relating to the converted signal point is used to find the decoding result of the received signal.
More concretely, the present invention provides a trellis decoder which employs a configuration comprising a signal conversion means for converting a received signal point into a converted signal point situated in any one of all quadrants on a complex plane specified by an I and an Q axis and for outputting the converted signal point and a quadrant signal representative of a quadrant where the received signal point is situated, a branch metric arithmetic means for deciding, by making use of the quadrant signal, the maximum likelihood between the converted signal point and a subset signal point and for outputting a branch metric and a subset decision signal, an ACS (Add Compare Selection) means for performing arithmetic operations to compute, from the branch metric, a path metric according to a trellis diagram and for outputting a path selection signal for selection of a path having a high likelihood, a first storage means for storing the quadrant signal, a second storage means for storing the subset decision signal, a third storage means for storing the path selection signal, a traceback means for performing, from a first to a second time point, traceback of the quadrant signal stored in the first storage means, the subset decision signal stored in the second storage means, and the path selection signal stored in the third storage means and for outputting a quadrant decoding signal based on the result of the quadrant signal traceback, a subset decoding signal based on the result of the subset decision signal traceback, and an encoded bit decoding signal based on the result of the path selection signal traceback, and a reverse conversion means for converting, by making use of the quadrant decoding signal, the subset decoding signal to provide a non-encoded bit decoding signal.
The traceback means and the reverse conversion means are replaceable with a traceback means for performing, from a first to a second time point, traceback of the quadrant signal stored in the first storage means, the subset decision signal stored in the second storage means, and the path selection signal stored in the third storage and for outputting a subset decoding signal based on the result of the quadrant signal traceback and on the result of the subset decision signal traceback and an encoded bit decoding signal based on the result of the path selection signal traceback, and with a reverse conversion means for converting the subset decoding signal to provide a non-encoded bit decoding signal, respectively.
The signal conversion means performs signal point conversion either by making utilization of foldback with respect to the I axis and/or the Q axis, or by making utilization of any one of a 90, a 180, and a 270 degree rotation centered on the origin of the complex plane.
The branch metric arithmetic means performs maximum likelihood decision either by the Hamming distance or by the Euclidean distance. The use of the Euclidean distance makes it possible to decide the maximum likelihood at higher accuracy.